STA Engineer Vacancy In Samsung : Samsung India has Invited online application form for the post of STA Engineer . the company offers challenges to work in multi-site environment on design and STA of complex IP cores at advanced technology nodes.
Applications for this post will be accepted only online, so candidates should take care of this. Please read the notification carefully before apply for this post. All the eligibility details are mentioned below. Kindly read all the details carefully before apply for this particular job.
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STA Engineer Vacancy In Samsung Details
| Post name | STA Engineer |
| Job Type | Full Time |
| Country | India |
| Company | Samsung |
| Job Location | Bangalore (India) |
| Qualification | BSEE or MSEE in EE with 10+ years of experience |
| Language Known | English/Hindi |
Qualification
Having BSEE or MSEE in EE with 10+ years of experience n the following area which is mention below
- CPU Cores custom design/ IP blocks high speed interface
- Top/block level Synthesis, Timing closure (STA)
- Having experience in DCT/DCG Based Synthesis
- Having experience in using Primetime SI and CCD/GCA
- Good knowledge and understanding of Deep Sub Micron topics
- Having experience in static timing flows, Formal checking, ASIC Synthesis flow etc.
- Having knowledge of DDR2/3/4/LPDDR2/3/4/AMBA (AXI, AHB and APB) protocols and DDR PHY interface (DFI) standard is a plus
- Having Knowledge of APR flows
Job Responsibility
- It includes developing of create micro-architecture, detailed design documents, architecture
- RTL design and custom digital design of the critical high speed Hard macro blocks
- Synthesis and DFT of the critical high speed Hard macro blocks
- must familiar with custom digital design (high speed logic paths)
- Timing closure of the critical high speed Hard macro blocks working with the BE team
- work to Develop floor-planning and CTS guidelines for layout
- Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, and work closely with layout engineers to achieve critical high speed path timing closure
- Perform in-house quality check before P&R and after P&R
- Power domain checks, CLP
- Work closely with analog and validation teams to bring up silicon and fine tune and debug performance issues at high speed
- Working on GLS closure with DV, PD and Modeling folks to ensure critical performance as well as timing paths are met and if some aspect of synch design techniques are used they are also validated well
- Supporting the SoC teams and customers in seamless integration the IP
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